Nowick Developing New Desktop Supercomputer
Professor Steven M. Nowick of the Departments of Computer Science and Electrical Engineering has received a large-scale National Science Foundation team grant to support his research in asynchronous (clockless) systems in computing. "This approach represents a paradigm shift from serial to parallel processing," says Nowick. "We expect that this grant will help us create the first-of-its-kind partly-asynchronous high-end massively-parallel on-chip computer." This grant is one of only two large-scale team proposals awarded by NSF under the "Design Automation for Micro and Nano Systems" topical area for its CPA program solicitation.
"All major commercial processor vendors are now committed to increasing the number of processors (cores) that fit on a single chip," says Nowick, "but there are major obstacles of power consumption, performance and scalability in existing synchronous design methodologies. This grant focuses on a particular existing easy-to-program and easy-to-teach multi-core architecture, and identifies the interconnection network, connecting multiple processor cores and memories, as the critical bottleneck to achieving lower over-all power consumption." Initial phases of this work were supported by seed funding from the Columbia Office of the Executive Vice President of Research, under an Initiatives in Science and Engineering (ISE) grant.
Nowick's NSF grant of almost $1 million will allow him to create a hybrid system that is part asynchronous and part synchronous. The goal is to build a robust and adaptive asynchronous mesh to link the various synchronous processor cores and memories. The asynchronous mesh--unlike current standard industry approaches, which are typically based on a single global clock rate--will allow easy modular integration of cores and memories operating at different clock rates, or dynamically-varying rates. This "elastic" digital communication fabric is also expected to have significantly lower power, because no high-speed clock will be distributed across the mesh. Also, dynamic power will only be consumed on demand as data items progress through the mesh; in contrast, synchronous communication meshes typically require regular clocking even of inactive routing nodes, thereby performing unnecessary work. This hybrid approach could push the level of scalability beyond what it currently possible and have a broad impact in supporting parallel applications in much of computer science and engineering.
"We will create a parallel architecture that will be globally-asynchronous and locally-synchronous (GALS), which will accommodate synchronous cores and memories that operate at arbitrary, unrelated clock rates," says Nowick. "This will provide robustness to timing variability and support for plug-and-play (i.e., scalable) system design."
Professor Uzi Vishkin of the University of Maryland is co-Principal Investigator and, Nowick says, the two research groups also will develop CAD (computer-aided design) tools to support the design of this new high-speed asynchronous communication mesh, and will develop analysis tools to be applied to the entire parallel structure. In addition, the work will be in collaboration with a separate NSF proposal under the direction of Professor Ken Stevens of the University of Utah. The two proposals will be linked together into a larger framework; the Utah group will refine their commercial-based physical design tool development and support, while the Columbia/Maryland group will provide a new substantial test case for their asynchronous tool applications.
This work will have a broad impact, says Nowick, because, although targeted to one style of shared-memory parallel architecture, several other architectures will benefit, since the interconnection network can be applied to them as well. In addition, the work is expected to demonstrate the benefits and role of asynchronous design for complex high-performance systems.
