CS Distinguished Lecture - Joel Emer
Online Lecture

ABSTRACT
Recent history is replete with myriad examples of new applications that have changed the course of computing and the world. These include the spreadsheet, visual editing, graphics, networking, and many more. Behind each of these advances were programs developed on easily-programmable and ever-faster processors. Unfortunately, as is widely acknowledged, the technological trend articulated by Moore's Law, which contributed significantly to creating the "ever faster" part of that recipe, is dead (or at least slowing significantly). However, as outlined in our "Science" article, "There's plenty of room at the top", there is promise in continuing Moore's Law-like improvements through a multi-pronged approach that includes software performance engineering, algorithm improvements and hardware architecture advances. Among those researchers focusing on the hardware architecture advances prong, there are many who advocate significant specialization of the hardware to specific domains, which will typically be well-understood and of widely-acknowledged importance. This approach, however, is likely to impede the development of the next big application because there will be no generally-programmable platform on which to develop it. Therefore, I believe that the biggest challenge in evolving hardware architectures in the post-Moore era lies in striking the right balance between preserving broad programmability and enhancing efficiency. In this talk, I will discuss how we have approached that challenge by focusing on the aspects of the hardware that gives the most leverage to improve efficiency and by providing an abstraction that makes it possible to compile to the new hardware. More specifically, since data movement has become the dominant consumer of energy, I will describe structures that facilitate "data orchestration" that reduce and optimize data movement. I also will describe abstractions that are intended to make it possible to compile high-level programs to these new hardware structures.

BIO
For over 40 years, Joel Emer held various research and advanced development positions investigating processor microarchitecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha, and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of deep learning accelerator design, spatial and parallel architectures, processor reliability analysis, cache organization, and simultaneous multithreading. Currently, he is a professor at the Massachusetts Institute of Technology and spends part-time as a Senior Distinguished Research Scientist in Nvidia's Architecture Research group. Previously, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Even earlier, he worked at Compaq and Digital Equipment Corporation. He earned a doctorate in electrical engineering from the University of Illinois in 1979. He received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. Recognitions of his contributions include an ACM/SIGARCH-IEEE-CS/TCCA Most Influential Paper Award for his work on simultaneous multithreading and six other papers that were selected as IEEE Micro's Top Picks in Computer Architecture. Among his professional honors, he is a Fellow of both the ACM and IEEE, and a member of the NAE. In 2009 he was the recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.

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