Portrait of Prof. James Teherani  

James T. Teherani


Northwest Corner Building
Room 1007

Tel(214) 435-9761

Teherani’s research interests span semiconductor materials and devices with the goal of explaining semiconductor device physics through modeling, simulation, and experiment. His group conducts both theoretical and experimental work—from quantum-mechanical simulations to nanoscale fabrication. His previous work has studied strain engineering, high-mobility transistors (MOSFETs), tunneling transistors (TFETs), and metal-insulator-semiconductor interfaces in the strained-Si, strained-Ge, InAs, and GaSb material systems.

Teherani joined Columbia University as an assistant professor in the Department of Electrical Engineering in 2015. He received his BS in electrical and computer engineering from the University of Texas at Austin in 2008, and his SM and PhD degrees in electrical engineering and computer science from the Massachusetts Institute of Technology in 2010 and 2015. He was a co-recipient of the 2014 George E. Smith Award for best paper in IEEE Electron Device Letters for his work on record-high hole mobility in strained-Ge MOSFETs. He is currently serving on the Nanotechnology Committee of the IEEE Electron Devices Society.


  • Postdoctoral associate, electrical engineering and computer science, Massachusetts Institute of Technology (MIT), 2015
  • Semiconductor device physics graduate researcher, electrical engineering and computer science, MIT, 2008-2015
  • Device physics intern, IBM Research, T. J. Watson Research Center, Yorktown Heights, New York, Summer 2009
  • Engineering intern, DRS Infrared Technologies, Dallas, Texas, Summer 2005, 2007


  • Assistant professor of electrical engineering, Columbia University, 2015—present


  • Institute of Electrical and Electronics Engineers (IEEE)
  • IEEE Electron Device Society, Nanotechnology Committee


  • National Science Foundation Graduate Fellowship, 2010 – 2015
  • George E. Smith Award (best paper in IEEE Electron Device Letters journal), 2014
  • National Defense Science and Engineering Graduate Fellowship (NDSEG)       , 2010 – 2013
  • National Nanotechnology Infrastructure Network (NNIN) International Winter School Fellow, 2011
  • University of Texas, Engineering Foundation Undergraduate Endowed Presidential Scholarship, 2007
  • University of Texas, B. N. Gafford Scholarship in Electrical and Computer Engineering, 2006
  • DRS Technologies Academic Scholarship, 2006



  • Kerelsky, A. Nipane, D. Edelberg, D. Wang, M. Cheng, A. Dadgar, H. Gao, K. Kang, J. Park, J. Teherani, and A. Pasupathy, “Band Structure Evolution in Vertically Contacted MoS2 Probed Using Scanning Tunneling Spectroscopy,” in Bulletin of the American Physical Society, vol. Volume 62, Number 4, March 2017.
  • J. Teherani, S. Agarwal, W. Chern, P. Solomon, E. Yablonovitch, and D. Antoniadis, “Auger generation as an intrinsic limit to tunneling field-effect transistor performance,” Journal of Applied Physics, vol. 120, no. 8, p. 084507, Aug. 2016.
  • S. Agarwal, J. Teherani, J. Hoyt, D. Antoniadis, and E. Yablonovitch. "Engineering the Electron-Hole Bilayer Tunneling Field-Effect Transistor," IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1599–1606, April 2014.
  • W. Chern, P. Hashemi, J. Teherani, D. Antoniadis, and J. Hoyt, "Record Hole Mobility at High Vertical Fields in Planar Strained Germanium on Insulator with Asymmetric Strain," IEEE Electron Device Letters, vol. 35, no. 3, pp. 309–311, March 2014.
  • T. Yu, J. Teherani, D. A. Antoniadis, and J. Hoyt, “InGaAs/GaAsSb Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics,” IEEE Electron Device Letters, vol. 34, no. 12, pp. 1503–1505, Dec. 2013.
  • J. Teherani, W. Chern, D. Antoniadis, and J. Hoyt, “Simulation of Enhanced Hole Ballistic Velocity in Asymmetrically Strained Germanium Nanowire Trigate p-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), 2013, pp. 32.4.1–32.4.4.
  • J. Teherani, S. Agarwal, E. Yablonovitch, J. Hoyt, and D. Antoniadis, “Impact of Quantization Energy and Gate Leakage in Bilayer Tunneling Transistors,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 298–300, Feb. 2013.
  • W. Chern, P. Hashemi, J. Teherani, T. Yu, Y. Dong, G. Xia, D. Antoniadis, and J. Hoyt, “High mobility high-K-all-around asymmetrically-strained Germanium nanowire trigate p-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), 2012, pp. 16.5.1–16.5.4.
  • J. Teherani, W. Chern, D. Antoniadis, J. Hoyt, L. Ruiz, C. Poweleit, and J. Menéndez, “Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates,” Phys. Rev. B, vol. 85, no. 20, p. 205308, May 2012.
  • P. Hashemi, J. Teherani, and J. Hoyt, “Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal-gate: effects of hydrogen thermal annealing and nanowire shape,” IEEE International Electron Device Meeting (IEDM), 2010, pp. 34.5.1–34.5.4.