Luca Carloni


466 Computer Science Building
Mail Code 0401

Tel(212) 939-7043
Fax(212) 666-0140

Luca Carloni creates and develops system architectures and design technologies for heterogeneous computing. Heterogeneity is the key to both high performance and energy efficiency. Examples of heterogeneous computing platforms range from the systems-on-chip that are at the core of smartphones and automotive electronics to the high-performance servers that empower the data centers in the cloud. 

Research Interests

System-on-Chip (SoC) Platforms, Embedded Systems, System-Level Design, Computer-Aided Design.

Carloni has made research contributions across all main aspects of engineering these computing platforms, including system architecture, hardware design, software programming, networking, power management, rapid prototyping, system-level design methodologies, and computer-aided design (CAD) tools.

Most recently, Carloni has proposed and developed Embedded Scalable Platforms (ESP) as a novel approach to help engineering teams cope with the complexity challenges of designing and programming billion-transistor system-on-chip architectures, which integrate an increasing number of general-purpose processor cores and specialized hardware accelerators.  ESP combines an architecture and a methodology. The flexible socketed architecture simplifies the integration of heterogeneous components by balancing regularity and specialization and eases the realization of prototypes with Field-Programmable Gate Arrays (FPGA) technologies. The companion methodology improves the productivity and collaboration among software programmers and hardware engineers, by raising the level of abstraction to system-level design, promoting the use of high-level synthesis, and enabling the reuse of predesigned components. Carloni’s research has informed his teaching activities at Columbia, particularly with the development of the two new courses “System-on-Chip Platforms” and “Embedded Scalable Platforms.”

Carloni received a BS in electrical engineering from the University of Bologna, Italy in 1995, an MS in Engineering from the University of California, Berkeley, in 1997, and a PhD in electrical engineering and computer science from the University of California, Berkeley, in 2004. In 2004, he joined the faculty of Columbia Engineering. He is a fellow of the Institute of Electrical and Electronics Engineers.


  • Associate Professor of Computer Science, Columbia University, 2009–
  • Assistant Professor of Computer Science, Columbia University, 2004–2008


  • Association for Computing Machinery (ACM)
  • Institute of Electrical and Electronics Engineers (IEEE) 


  • Fellow, Institute of Electrical and Electronics Engineers (IEEE), 2017
  • Office of Naval Research (ONR) Young Investigator Award, 2010
  • Research Fellow, Alfred P. Sloan Foundation, 2008
  • NSF Faculty Early Career Development (CAREER) Award, 2006


  • L. P. Carloni. The Case for Embedded Scalable Platforms. Invited Paper. In Proceedings of the Design Automation Conference (DAC), pages 17:1-17:6, Austin, TX, June 2016.
  • P. Mantovani, E. G. Cota, K. Tien, C. Pilato, G. Di Guglielmo, K. Shepard, and L. P. Carloni. An FPGA-Based Infrastructure for Fine-Grained DVFS Analysis in High-Performance Embedded Systems. In Proceedings of the Design Automation Conference (DAC), pages 157:1-157:6, Austin, TX, June 2016.
  • L. P. Carloni. From Latency-Insensitive Design to Communication-Based System-Level Design. Proceedings of the IEEE, 103(11):2133-2151, November 2015.
  • H.-Y. Liu, M. Petracca, and L. P. Carloni. Compositional System-Level Design Exploration with Planning of High-Level Synthesis. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pages 641-646, Dresden, Germany, March 2012.
  • N. Sturcken, E. J. O'Sullivan, N. Wang, P. Herget, B. Webb, L. T. Romankiw, M. Petracca, R. Davies, R. Fontana, G. M. Decad, I. Kymissis, A. V. Peterchev, L. P. Carloni, W. J. Gallagher, and K. L. Shepard. A 2.5D Integrated Voltage Regulator Using Coupled Magnetic Core Inductors on Silicon Interposer Delivering 10:8A/mm2. In ISSCC Digest of Technical Papers, pages 400-402, February 2012.
  • J. Chan, G. Hendry, K. Bergman, and L. P Carloni. Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(10):1507-1520, October 2011.
  • A. Shacham, K. Bergman, and L. P. Carloni. Photonic Networks-on-Chip for Future Generations of Chip Multi-Processors. IEEE Transactions on Computers, 57(9):1246-1260, September 2008.
  • L. P. Carloni and A. L. Sangiovanni-Vincentelli. Coping with Latency in SOC Design. IEEE Micro, 22(5):24-35, Sep-Oct 2002.
  • L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli. Theory of Latency-Insensitive Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1059-1076, September 2001.
  • L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sangiovanni-Vincentelli. A Methodology for “Correct-by-Construction” Latency Insensitive Design. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pages 309-315, San Jose, CA, November 1999.